It is well known that capacitors can be created between layers of metal or polysilicon. Capacitors can either have a planar design, for reasons of process simplicity, or can have a three-dimensional design, resulting in a smaller footprint as commonly used in embedded dynamic random access memory (eDRAM) devices.
eDRAM devices typically consist of arrays of memory cells that perform two basic functions, particularly data access control performed by a transistor and also data retention performed by a capacitor. Binary data is stored as electrical charges in the capacitors in eDRAM memory cells. Contacts to the surrounding circuits are provided to the eDRAM memory cells. Due to leakage currents, eDRAM cells can retain information only for a limited period of time before they must be read and refreshed periodically. In a typical eDRAM construction, one side of the transistor is connected to one side of the capacitor, and the other side of the capacitor is connected to a reference voltage.
The capacitors used in the eDRAM memory cells are commonly referred to as metal-insulator-metal (MIM) capacitors. As is well known in the art, the capacitances of capacitors are related to the areas of the capacitors and the thicknesses and the dielectric constants (k values) of the insulators. To increase the capacitances of the capacitors, insulators preferably have high k values. However, in 90 nm and 65 nm technologies, the thicknesses of the insulators are typically below 100 Å, and in the reliability tests, capacitors having high-k insulators with such thicknesses only marginally passed the time dependent dielectric breakdown (TDDB) test. In future generations of integrated circuits, the thicknesses of the high-k insulators will continue to be scaled down. This will cause further reduction in TDDB lifetime, and hence the reliability of capacitors may not even pass the TDDB test. Accordingly, new capacitor structures and formation methods are needed.